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1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com hi-reliability product WEDPN8M72V-133BC october 2000 rev. 0 general description the 64mbyte (512mb) sdram is a high-speed cmos, dynamic random-access ,memory using 5 chips containing 134,217,728 bits. each chip is internally configured as a quad-bank dram with a synchronous interface. each of the chips 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a pro- grammed number of locations in a programmed sequence. ac- cesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba 0 , ba 1 select the bank; a 0-11 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. the sdram provides for programmable read or write burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self- timed row precharge that is initiated at the end of the burst sequence. the 512mb sdram uses an internal pipelined architecture to achieve high-speed operation. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high- speed, random-access operation. the 512mb sdram is designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided, along with a power-saving, power-down mode. all inputs and outputs are lvttl compatible. sdrams offer substan- tial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with automatic column- address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. 8mx72 synchronous dram preliminary* features n high frequency = 133mhz (cl3) or 100mhz (cl2) n package: ? 219 plastic ball grid array (pbga), 32 x 25mm n single 3.3v 0.3v power supply n fully synchronous; all signals registered on positive edge of system clock cycle n internal pipelined operation; column address can be changed every clock cycle n internal banks for hiding row access/precharge n programmable burst length 1,2,4,8 or full page n 4096 refresh cycles n commercial temperature range n organized as 8m x 72 n weight: WEDPN8M72V-133BC - 2.5 grams typical benefits n 40% space savings n reduced part count n reduced i/o count ? 19% i/o reduction n lower inductance and capacitance for low noise performance n suitable for hi-reliability applications n upgradeable to 16m x 72 density (contact factory for information) * this data sheet describes a product under development, not fully characterized, and is subject to change without notice. 32 25 discrete approach s a v i n g s area 5 x 265mm 2 = 1328mm 2 800mm 2 40% 5 x 54 pins = 270 pins 219 balls 19% actual size 22.3 11.9 11.9 i/o count 11.9 11.9 11.9
2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com WEDPN8M72V-133BC fig. 1 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a b c d e f g h j k l m n p r t dq 1 dq 3 dq 6 dq 7 cas 0 cs 0 v ss v ss nc nc dq 56 dq 57 dq 60 dq 62 vss v ss dq 30 dq 28 dq 25 dq 24 clk 1 cke 1 v cc v cc cs 2 cas 2 dq 39 dq 38 dq 35 dq 33 v cc dq 0 dq 2 dq 4 dq 5 dqml 0 we 0 ras 0 v ss v ss cke 3 clk 3 dqmh 3 dq 58 dq 59 dq 61 dq 63 dq 31 dq 29 dq 27 dq 26 nc dqmh 1 nc v cc v cc ras 2 we 2 dqml 2 dq 37 dq 36 dq 34 dq 32 dq 14 dq 12 dq 10 dq 8 v cc v cc v cc v cc v cc v cc v cc v cc dq 55 dq 53 dq 51 dq 49 dq 17 dq 19 dq 21 dq 23 v ss v ss v ss vss v ss v ss v ss v ss dq 40 dq 42 dq 44 dq 46 dq 15 dq 13 dq 11 dq 9 dqmh 0 clk 0 cke 0 v cc v cc cs 3 cas 3 we 3 dq 54 dq 52 dq 50 dq 48 dq 16 dq 18 dq 20 dq 22 dqml 1 we 1 cs 1 v ss v ss cke 2 clk 2 dqmh 2 dq 41 dq 43 dq 45 dq 47 v ss v ss v cc v cc nc nc nc v ss v ss nc ras 3 dqml 3 nc v ss v cc v cc v cc v cc v ss v ss nc ras 1 cas 1 v cc v cc nc nc cs 4 nc v cc v ss v ss a 9 a 0 a 2 dnu nc dqmh 4 dq 73 dq 75 dq 77 dq 79 a 8 a 1 a 3 dnu nc we 4 dq 70 dq 68 dq 66 dq 64 a 10 a 7 a 5 dnu ba 0 clk 4 dq 72 dq 74 dq 76 dq 78 a 11 a 6 a 4 dnu ba 1 cas 4 dq 71 dq 69 dq 67 dq 65 v ss v ss v cc v cc nc cke 4 nc v ss v cc v cc v cc v cc v ss v ss nc ras 4 dqml 4 v cc v ss v ss note: dnu = do not use; to be left unconnected for future upgrades. nc = not connected internally. top view
3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com WEDPN8M72V-133BC fig. 2 functional block diagram a 0-11 a 0-11 ba 0-1 ba 0-1 clk 0 clk cas dq 0 dq 15 cke 0 cke cs 0 cs dqml 0 dqml dqmh 0 dqmh ras 1 we 1 cas 1 dq 0 dq 15 we u1 ras a 0-11 ba 0-1 clk 1 clk cas dq 16 dq 31 ras 0 we 0 cas 0 dq 0 dq 15 we u0 ras cke 1 cke cs 1 cs dqml 1 dqml dqmh 1 dqmh ras 2 we 2 cas 2 dq 0 dq 15 we u2 ras a 0-11 ba 0-1 clk 2 clk cas dq 32 dq 47 cke 2 cke cs 2 cs dqml 2 dqml dqmh 2 dqmh ras 3 we 3 cas 3 dq 0 dq 15 we u3 ras a 0-11 ba 0-1 clk 3 clk cas dq 48 dq 63 cke 3 cke cs 3 cs dqml 3 dqml dqmh 3 dqmh ras 4 we 4 cas 4 dq 0 dq 15 we u4 ras a 0-11 ba 0-1 clk 4 clk cas dq 64 dq 79 cke 4 cke cs 4 cs dqml 4 dqml dqmh 4 dqmh
4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com WEDPN8M72V-133BC functional description read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a pro- grammed number of locations in a programmed sequence. ac- cesses begin with the registration of an active command which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba 0 and ba 1 select the bank, a 0-11 select the row). the address bits (a 0-8 ) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions and de- vice operation. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. once power is applied to v dd and v ddq (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100 m s delay prior to issuing any command other than a command inhibit or a nop. starting at some point during this 100 m s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 100 m s delay has been satisfied with at least one com- mand inhibit or nop command having been applied, a precharge command should be applied. all banks must be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be per- formed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. register definition mode register the mode register is used to define the specific mode of opera- tion of the sdram. this definition includes the selec-tion of a burst length, a burst type, a cas latency, an operating mode and a write burst mode, as shown in figure 3. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 specifies the type of burst (sequential or interleaved), m4-m6 specify the cas latency, m7 and m8 specify the operating mode, m9 speci- fies the write burst mode, and m10 and m11 are reserved for future use. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in figure 3. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a 1-8 when the burst length is set to two; by a 2-8 when the burst length is set to four; and by a 3-8 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 1.
5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com WEDPN8M72V-133BC table 1 - burst definition burst starting column order of accesses within a burst length address a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-9/8/7 cn, cn + 1, cn + 2 page cn + 3, cn + 4... not supported (y) (location 0-y) cn - 1, cn notes: 1. for full-page accesses: y = 512. 2. for a burst length of two, a 1-8 select the block-of-two burst; a0 selects the starting column within the block. 3. for a burst length of four, a 2-8 select the block-of-four burst; a 0-1 select the starting column within the block. 4. for a burst length of eight, a 3-8 select the block-of-eight burst; a 0-2 select the starting column within the block. 5. for a full-page burst, the full row is selected and a 0-8 select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a 0-8 select the unique column to be accessed, and mode register bit m3 is ignored. type = sequential type = interleaved fig. 3 mode register definition m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas lat ency bt a 9 a 7 a 6 a 5 a 4 a 3 a 8 a 2 a 1 a 0 mode register (mx) address bus m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a 10 a 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m11, m10 = 0, 0 to ensure compatibility with future devices.
6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com WEDPN8M72V-133BC cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n +m. the i/ os will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the i/os will start driving after t1 and the data will be valid by t2. table 2 below indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by setting m7and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because table 2 - cas latency fig. 4 cas latency allowable operating frequency (mhz) cas cas speed latency = 2 latency = 3 133 100 133 clk i/o t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don? care undefined clk i/o t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single- location (nonburst) accesses. commands the truth table provides a quick reference of available com- mands. this is followed by a written description of each com- mand. three additional truth tables appear following the opera- tion section; these tables provide current state/next state infor- mation.
7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com WEDPN8M72V-133BC truth table - commands and dqm operation (note 1) name (function) cs ras cas we dqm addr i/os command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) ( 3) l l h h x bank/row x read (select bank and column, and start read burst) (4) l h l h l/h 8 bank/col x write (select bank and column, and start write burst) (4) l h l l l/h 8 bank/col valid burst terminate l h h l x x active precharge (deactivate row in bank or banks) ( 5) l l h l x code x auto refresh or self refresh (enter self refresh mode) (6, 7) l l l h x x x load mode register (2) l l l l x op-code x write enable/output enable (8) C C C C l C active write inhibit/output high-z (8) C C C C h C high-z notes: 1. cke is high for all commands shown except self refresh. 2. a 0-11 define the op-code written to the mode register. 3. a 0-11 provide row address, and ba 0 , ba 1 determine which bank is made active. 4. a 0-8 provide column address; a 10 high enables the auto precharge feature (nonpersistent), while a 10 low disables the auto precharge feature; ba 0 , ba 1 determine which bank is being read from or written to. 5. a 10 low: ba 0 , ba 1 determine the bank being precharged. a 10 high: all banks precharged and ba 0 , ba 1 are dont care. 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are dont care except for cke. 8. activates or deactivates the i/os during writes (zero-clock delay) and reads (two-clock delay). read the read command is used to initiate a burst read access to an active row. the value on the ba 0 , ba 1 inputs selects the bank, and the address provided on inputs a 0-8 selects the starting column location. the value on input a 10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read data appears on the i/os subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the corresponding i/os will be high-z two clocks later; if the dqm signal was registered low, the i/os will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba 0 , ba 1 inputs selects the bank, and the address provided on inputs a 0-8 selects the starting column location. the value on input a 10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the i/os is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. command inhibit the command inhibit function prevents new commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively deselected. opera- tions already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram which is selected (cs is low). this prevents unwanted commands from being registered during idle or wait states. op- erations already in progress are not affected. load mode register the mode register is loaded via inputs a 0-11 . see mode register heading in the register definition section. the load mode register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba 0 , ba 1 inputs selects the bank, and the address provided on inputs a 0-11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank.
8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com WEDPN8M72V-133BC precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is issued. input a 10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba 0 , ba 1 select the bank. otherwise ba 0 , ba 1 are treated as dont care. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature which performs the same indi- vidual-bank precharge function described above, without re- quiring an explicit command. this is accomplished by using a 10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst, except in the full- page burst mode, where auto precharge does not apply. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time (t rp ) is completed. this is determined as if an explicit precharge com- mand was issued at the earliest possible time. burst terminate the burst terminate command is used to truncate either fixed- length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated. auto refresh auto refresh is used during normal operation of the sdram and is analagous to cas-before-ras (cbr) refresh in conven- tional drams. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits dont care during an auto refresh command. each 128mb sdram requires 4,096 auto refresh cycles every refresh period (t ref ). providing a distributed auto re- fresh command will meet the refresh requirement and ensure that each row is refreshed. alternatively, 4,096 auto refresh com- mands can be issued in a burst at the minimum cycle rate (t rc ), once every refresh period (t ref ). self refresh the self refresh command can be used to retain data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). once the self refresh command is registered, all the inputs to the sdram become dont care, with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram provides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to cke going back high. once cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr , because time is required for the completion of any internal refresh in progress. upon exiting the self refresh mode, auto refresh commands must be issued as both self refresh and auto refresh utilize the row refresh counter.
9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com WEDPN8M72V-133BC dc electrical characteristics and operating conditions (notes 1, 6) (v cc = +3.3v 0.3v; t a = 0 c to +70 c) parameter/condition symbol units min max supply voltage v cc 3 3.6 v input high voltage: logic 1; all inputs (21) v ih 2v cc + 0.3 v input low voltage: logic 0; all inputs (21) v il -0.3 0.8 v input leakage current: any input 0v v in v cc (all other pins not under test = 0v) i i -5 5 m a input leakage address current (all other pins not under test = 0v) i i -25 25 m a output leakage current: i/os are disabled; 0v v out v cc i oz -5 5 m a output levels: output high voltage (i out = -4ma) v oh 2.4 C v output low voltage (i out = 4ma) v ol C 0.4 v absolute maximum ratings parameter unit voltage on v dd , v ddq supply relative to vss -1 to 4.6 v voltage on nc or i/o pins relative to vss -1 to 4.6 v operating temperature t a (coml) 0 to +70 c storage temperature, plastic -55 to +150 c power dissipation 5 w note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional opera- tion of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (note 2) parameter symbol max unit input capacitance: clk c i1 10 pf addresses, ba 0-1 input capacitance ca 30 pf input capacitance: all other input-only pins c i2 10 pf input/output capacitance: i/os c io 12 pf i cc specifications and conditions (notes 1,6,11,13) (v cc = +3.3v 0.3v; t a = 0 c to +70 c) parameter/condition symbol max units operating current: active mode; i cc1 750 ma burst = 2; read or write; t rc = t rc (min); cas latency = 3 (3, 18, 19) standby current: active mode; cke = high; cs = high; i cc3 250 ma all banks active after t rcd met; no accesses in progress (3, 12, 19) operating current: burst mode; continuous burst; i cc4 750 ma read or write; all banks active; cas latency = 3 (3, 18, 19) self refresh current: cke 0.2v (commercial temperature: 0 c to +70 c) i cc7 10 ma
10 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com WEDPN8M72V-133BC parameter symbol -100 133 unit min max min max access time from clk (pos. edge) cl = 3 t ac 6 5.4 ns cl = 2 t ac 6ns address hold time t ah 1 0.8 ns address setup time t as 2 1.5 ns clk high-level width t ch 3 2.5 ns clk low-level width t cl 3 2.5 ns clock cycle time (22) cl = 3 t ck 8 7.5 ns cl = 2 t ck 10 ns cke hold time t ckh 1 0.8 ns cke setup time t cks 2 1.5 ns cs, ras, cas, we, dqm hold time t cmh 1 0.8 ns cs, ras, cas, we, dqm setup time t cms 2 1.5 ns data-in hold time t dh 1 0.8 ns data-in setup time t ds 2 1.5 ns data-out high-impedance time cl = 3 (10) t hz 6 5.4 ns cl = 2 (10) t hz 7ns data-out low-impedance time t lz 11ns data-out hold time (load) t oh 3 2.7 ns data-out hold time (no load) (26) t oh n 1.8 1.8 ns active to precharge command t ras 50 120,000 44 120,000 ns active to active command period t rc 70 66 ns active to read or write delay t rcd 20 20 ns refresh period (4,096 rows) C commercial t ref 64 64 ms auto refresh period t rfc 70 66 ns precharge command period t rp 20 20 ns active bank a to active bank b command t rrd 15 15 ns transition time (7) t t 0.3 1.2 0.3 1.2 ns write recovery time (23) t wr 1 clk + 7ns 1 clk + 7.5ns (24) 15 15 ns exit self refresh to active command t xsr 80 75 ns electrical characteristics and recommended ac operating characteristics (notes 5, 6, 8, 9, 11)
11 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com WEDPN8M72V-133BC ac functional characteristics (notes 5,6,7,8,9,11) parameter/condition symbol -100 -133 units read/write command to read/write command (17) t ccd 11t ck cke to clock disable or power-down entry mode (14) t cked 11t ck cke to clock enable or power-down exit setup mode (14) t ped 11t ck dqm to input data delay (17) t dqd 00t ck dqm to data mask during writes t dqm 00t ck dqm to data high-impedance during reads t dqz 22t ck write command to input data delay (17) t dwd 00t ck data-in to active command (15) t dal 45t ck data-in to precharge command (16) t dpl 22t ck last data-in to burst stop command (17) t bdl 11t ck last data-in to new read/write command (17) t cdl 11t ck last data-in to precharge command (16) t rdl 22t ck load mode register command to active or refresh command (25) t mrd 22t ck data-out to high-impedance from precharge command (17) cl = 3 t roh 33t ck cl = 2 t roh 2t ck notes: 1. all voltages referenced to v ss . 2. this parameter is not tested but guaranteed by design. f = 1 mhz, t a = 25 c. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. an initial pause of 100ms is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v cc must be powered up simultaneously.) the two auto refresh command wake-ups should be repeated any time the t ref refresh require- ment is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5v with equivalent load: 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. q 50pf 12. other input signals are allowed to transition no more than once every two clocks and are otherwise at valid v ih or v il levels. 13. i cc specifications are tested after the device is properly initialized. 14. timing actually specified by t cks ; clock(s) specified as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp ; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr . 17. required clocks are specified by jedec functionality and are not depen- dent on any timing parameter. 18. the i cc current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 19. address transitions average one transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. v ih overshoot: v ih (max) = v cc + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 3ns. 22. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, including t wr , and precharge commands). cke may be used to reduce the data rate. 23. auto precharge mode only. the precharge timing budget (t rp ) begins 7.5ns/7ns after the first clock delay, after the last write is executed. 24. precharge mode only. 25. jedec and pc100 specify three clocks. 26. parameter guaranteed by design.
12 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com WEDPN8M72V-133BC wed p n 8m 72 v - 133 b c package dimension: 219 plastic ball grid array (pbga) all linear dimensions are millimeters and parenthetically in inches ordering information device grade: c = commercial 0 c to +70 c package: b = 219 plastic ball grid array (pbga) frequency (mhz) 133 = 133mhz 3.3v power supply configuration, 8m x 72 sdram plastic white electronic designs corp. bottom view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t r p n m l k j h g f e d c b a 219 x ? 0.835 1.27/2 1.27 (0.050) bsc 1.27/2 32.32 (1.272) max 25.25 (0.994) max 2.34 (0.092) max 0.60 (0.024) 0.10 (0.004) 19.05 (0.750) nom 19.05 (0.750) nom

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